A DESIGN METHODOLOGY FOR LOW-LEAKAGE AND HIGH-PERFORMANCE BUFFER BASED ON DEVIANT BEHAVIOR OF GATE LEAKAGE

摘要

Based on the observation that both subthreshold and gate leakage depend on transistors width, this paper introduces a feasible method to fast estimate leakage current in buffers. In simulating of leakage current with swept transistor width, we found that gate leakage is not always a linear function of the device geometry. Subsequently, this paper presented the theoretical analysis and experimental evidence of this exceptional gate leakage behavior and developed a design methodology to devise a low-leakage and high-performance buffer with no penalty in area using this deviation.