首页> 外国专利> METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BURIED GATE CAPABLE OF IMPROVING THE GAP-FILL MARGIN OF CONDUCTIVE MATERIALS BY FORMING A T-SHAPED RECESS PATTERN

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BURIED GATE CAPABLE OF IMPROVING THE GAP-FILL MARGIN OF CONDUCTIVE MATERIALS BY FORMING A T-SHAPED RECESS PATTERN

机译:制造具有埋入式浇口的半导体器件的方法,该埋入式浇口能够通过形成T形的回弹图案来改善导电材料的间隙填充余量

摘要

PURPOSE: A method for manufacturing a semiconductor device with a buried gate is provided to improve the uniformity of a fin and a channel length by etching a recess pattern twice.;CONSTITUTION: A device isolation layer(11) is formed on a substrate(10) through an STI(Shallow Trench Isolation). A first hard mask layer and a second hard mask layer are laminated on the substrate. A reflection preventing layer is laminated on the second hard mask layer. A spacer is formed on the sidewall of the reflection preventing layer and the first and second hard mask layers. A gate insulation layer(19) is formed on the lower side and the sidewall of the recess pattern. A buried gate(20) is formed on the gate insulation layer to fill the recess pattern with a preset depth.;COPYRIGHT KIPO 2012
机译:目的:提供一种用于制造具有掩埋栅的半导体器件的方法,以通过两次蚀刻凹槽图案来提高鳍片的均匀性和沟道长度。组成:器件隔离层(11)形成在衬底(10)上)通过STI(浅沟槽隔离)。在基板上层压第一硬掩模层和第二硬掩模层。防反射层被层压在第二硬掩模层上。在防反射层以及第一硬掩模层和第二硬掩模层的侧壁上形成隔离物。在凹陷图案的下侧和侧壁上形成栅极绝缘层(19)。在栅极绝缘层上形成掩埋栅极(20),以预设深度填充凹陷图案。; COPYRIGHT KIPO 2012

著录项

  • 公开/公告号KR20110103600A

    专利类型

  • 公开/公告日2011-09-21

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20100022741

  • 发明设计人 PARK JEUNG PYO;

    申请日2010-03-15

  • 分类号H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 17:51:05

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