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MOS TRANSISTOR INTEGRATED CIRCUIT AND SIMULATING CALCULATION SYSTEM OF DEGRADATION DEGREE OF MOS TRANSISTOR

机译:MOS晶体管集成电路及MOS晶体管退化度模拟计算系统

摘要

PROBLEM TO BE SOLVED: To solve such a problem that a system arranged so as to calculate a degradation degree of a MOS transistor for individual integrated circuit is not in existence up to this time although the quantitative grasp of degradation degree is required, because the degradation occurs in characteristics of the MOS transistor constituting a ring oscillator in a MOS transistor integrated circuit when the use period becomes long, and an oscillation frequency becomes extensive.;SOLUTION: The ring oscillator 4 configured to only occur the degradation of the NMOS transistor and the ring oscillator 5 configured to only occur the degradation of the PMOS transistor are made up in the MOS transistor integrated circuit 1 integrating the ring oscillator 2. The increased delay time due to the degradation or the oscillation period is calculated by a simulating calculation device 7 based on the oscillation period at the present time point or the oscillation period at the beginning of manufacture.;COPYRIGHT: (C)2013,JPO&INPIT
机译:解决的问题:尽管需要对劣化度进行定量把握,但是直到现在为止,仍不存在用于计算单个集成电路的MOS晶体管的劣化度而布置的系统的问题。当使用时间变长并且振荡频率变大时,在MOS晶体管集成电路中构成环形振荡器的MOS晶体管的特性就会发生。解决方案:环形振荡器4被配置为仅发生NMOS晶体管和晶体管的劣化。在集成了环形振荡器2的MOS晶体管集成电路1中,构成了仅使PMOS晶体管的劣化发生的环形振荡器5。通过模拟运算装置7,基于该劣化或振荡周期而增加了延迟时间。当前时间的振荡周期或制造开始时的振荡周期版权:(C)2013,JPO&INPIT

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