DESIGN DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a design device for easily minimizing the size of a retention register.SOLUTION: A design device of the present embodiment includes: a CDFG generation part; a scheduling part; a binding part; a retention register selection part; a control circuit generation part; and an RTL description generation part. The binding part generates a data path circuit in which a hardware element is allocated to a CDFG whose scheduling has been performed by the scheduling part. The retention register selection part detects a control step in which the number of bits of latch is minimized as a retention control step from the CDFG whose scheduling has been performed, and selects a register allocated to the detected retention control step as a retention register. The control circuit generation part generates a control circuit whose state is transited to the retention control step when a signal for power shutdown becomes valid.