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Method for wafer level packaging of integrated circuit dies, composite wafers obtained using the method and wafer level package

机译:集成电路管芯的晶片级封装的方法,使用该方法获得的复合晶片和晶片级封装

摘要

A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional "upper-level" cap wafers (with or without die) can be stacked to form a "multi-story" IC.
机译:晶片级封装的IC是通过在切割IC晶片之前(即,在IC晶片上分割多个管芯之前)将盖晶片附接到IC晶片的顶部而制成的。将盖晶片机械地附接并电连接至IC晶片,然后将管芯单个化。导电路径在盖的顶表面上的晶片接触垫与IC晶片上的电接触点之间延伸穿过盖晶片。可选地,盖晶片包含一个或多个管芯。可以根据与盖晶片不同的技术来制造IC晶片,从而形成混合晶片级封装。可选地,可以堆叠额外的“上层”盖晶片(具有或不具有管芯)以形成“多层” IC。

著录项

  • 公开/公告号JP4977388B2

    专利类型

  • 公开/公告日2012-07-18

    原文格式PDF

  • 申请/专利权人 メムシック;インコーポレイテッド;

    申请/专利号JP20060076894

  • 发明设计人 ヤン チャオ;

    申请日2006-03-20

  • 分类号H01L23/02;H01L23/14;H01L25/065;H01L25/07;H01L25/18;

  • 国家 JP

  • 入库时间 2022-08-21 17:40:47

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