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Method of semiconductor integrated circuit, recording medium recording design program of semiconductor integrated circuit, and design support apparatus of semiconductor integrated circuit

机译:半导体集成电路的方法,记录半导体集成电路的设计程序的记录介质以及半导体集成电路的设计支持装置

摘要

A design method of a semiconductor integrated circuit carried out by a computer, including: a DRC step of performing a design rule check (Design Rule Check) with reference to layout information on an internal wiring in a capacitor cell and layout information on a signal wiring in the semiconductor integrated circuit; an integration step of integrating layout information on the internal wiring into layout information on the signal wiring when being determined in the DRC step that there is an error; and an elimination step of eliminating an error portion in the internal wiring from the integrated layout information.
机译:由计算机执行的半导体集成电路的设计方法,包括:DRC步骤,其参考电容器单元中的内部布线上的布局信息和信号布线上的布局信息来执行设计规则检查(Design Rule Check)在半导体集成电路中;当在DRC步骤中确定存在错误时,将内部布线上的布局信息集成到信号布线上的布局信息的集成步骤;消除步骤是从综合布局信息中消除内部布线中的错误部分。

著录项

  • 公开/公告号US8225263B2

    专利类型

  • 公开/公告日2012-07-17

    原文格式PDF

  • 申请/专利权人 TAKASHI GOTOU;

    申请/专利号US20090408218

  • 发明设计人 TAKASHI GOTOU;

    申请日2009-03-20

  • 分类号G06F17/50;G06F9/455;G06F11/22;

  • 国家 US

  • 入库时间 2022-08-21 17:29:56

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