Common clock path pessimism analysis for circuit designs using clock tree networks

摘要

Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism. The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.