Clock network analysis at the pre-layout stage for efficient clock tree synthesis SOC design

摘要

In synchronous circuits, the design of clock distribution networks can affect system performance and reliability dramatically. The clock tree synthesis (CTS) requires a technique to distribute clock signals effectively in a system-on-a-chip (SOC) design. This paper presents the techniques to analyze the clock networks that include gated clocks and multiple clock roots, and provide the information required for the successful CTS. We also propose a novel method to increase the accuracy of delay and power estimation at the pre-layout stage. Consequently, the proposed techniques constitute a new CTS design flow that enables a designer to reduce the design cycle by fixing the critical problems before getting into the layout phase. In order to demonstrate the effectiveness of the proposed techniques, an experiment on a real ASIC design has been carried out.