首页> 外国专利> DIGITAL PLL(PHASE LOCKED LOOP) FOR HAVING CONSTANT JITTER CHARACTERISTICS INSENSITIVE TO OPERATING CIRCUMSTANCES

DIGITAL PLL(PHASE LOCKED LOOP) FOR HAVING CONSTANT JITTER CHARACTERISTICS INSENSITIVE TO OPERATING CIRCUMSTANCES

机译:数字PLL(锁相环),具有恒定的抖动特性,不敏感于操作情况

摘要

PURPOSE: A digital PLL(Phase Locked Loop) for having constant jitter characteristics insensitive to operating circumstances is provided to offset the change of total loop-dynamics according to the change of DCO(Digital Controlled Oscillator) characteristics by controlling a coefficient value of a digital loop filter.;CONSTITUTION: A digital PLL(Phase-Locked Loop) includes a digital converter(10), a DLF(Digital Loop Filter)(20), and a digital controlled oscillator(30). A digital TDC(Time-to-Digital Converter) performs the same function as a detector in an analog PLL. The digital converter outputs a digital signal in proportional to the phase difference and frequency difference between an output clock of a reference input clock and a first frequency divider(40). The DLF outputs a controlled control value to the digital controlled oscillator. The digital controlled oscillator generates an output clock.;COPYRIGHT KIPO 2012
机译:目的:提供一种数字PLL(锁相环),其具有对操作环境不敏感的恒定抖动特性,以通过控制数字的系数值来根据DCO(数字控制振荡器)特性的变化来补偿总环路动力学的变化。组成:数字PLL(锁相环)包括一个数字转换器(10),一个DLF(数字环路滤波器)(20)和一个数字控制振荡器(30)。数字TDC(时间数字转换器)执行与模拟PLL中的检测器相同的功能。该数字转换器输出与参考输入时钟的输出时钟和第一分频器(40)之间的相位差和频率差成比例的数字信号。 DLF将受控的控制值输出到数控振荡器。数字振荡器产生一个输出时钟。; COPYRIGHT KIPO 2012

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