An integrated circuit design method able to generate circuit data enabling a clear grasp of power switch cells and circuit cells whose power is cut off without obstructing the efficiency of the design, wherein in the description of RTL data generated at an RTL data generation unit (ST101), a hierarchical block of an upper level with a lower level comprised of a hierarchical block corresponding to a circuit whose power should be cut off in response to a control signal and a predetermined virtual power switch cell to which this control signal is input is prepared (ST103). By obtaining a grasp of the relationship between the virtual power switch cells in the description of the RTL data and the hierarchical blocks of the same level as the virtual power switch cells, the relationship between the power switch cells and the circuits whose power should be cut off in a real circuit can be clearly grasped. IMAGE
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