首页> 外国专利> 3D VERTICAL TYPE MEMORY CELL STRING WITH SHIELD ELECTRODE, MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF

3D VERTICAL TYPE MEMORY CELL STRING WITH SHIELD ELECTRODE, MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF

机译:带屏蔽电极的3D垂直型记忆细胞系,使用其的记忆阵列及其制造方法

摘要

PURPOSE: A three dimensional vertical memory cell string with a shield electrode, a memory array using the same, and a manufacturing method thereof are provided to improve integration by reducing the width of a trench between adjacent cell stacks. CONSTITUTION: Electrode stacks are formed by filling a selectively etched sacrificial semiconductor layer with an insulation layer. A gate insulation layer stack including a charge storage layer(3) is formed on each trench. A semiconductor body(5) is formed on the gate insulation layer stack. A separation insulation layer(6) is formed on each trench and surrounds the semiconductor body. A shield electrode(27) is formed on the separation insulation layer of each trench by depositing conductive materials on the semiconductor substrate and etching the semiconductor substrate.
机译:目的:提供一种具有屏蔽电极的三维垂直存储单元串,使用其的存储阵列及其制造方法,以通过减小相邻单元堆叠之间的沟槽的宽度来提高集成度。组成:电极堆是通过在绝缘层上填充选择性腐蚀的牺牲半导体层而形成的。在每个沟槽上形成包括电荷存储层(3)的栅绝缘层堆叠。在栅极绝缘层堆叠上形成半导体本体(5)。隔离绝缘层(6)形成在每个沟槽上并且围绕半导体本体。通过在半导体衬底上沉积导电材料并蚀刻半导体衬底,在每个沟槽的分离绝缘层上形成屏蔽电极(27)。

著录项

  • 公开/公告号KR101160185B1

    专利类型

  • 公开/公告日2012-06-26

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20100038691

  • 发明设计人 이종호;

    申请日2010-04-26

  • 分类号H01L21/8247;H01L27/115;

  • 国家 KR

  • 入库时间 2022-08-21 17:07:51

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