首页> 外国专利> 3D VERTICAL MEMORY CELL STRING WITH A WEIGHTING ELECTRODE TO INCREASE MEMORY CAPACITY, A MEMORY ARRAY USING THE SAME, AND A MANUFACTURING METHOD THEREOF

3D VERTICAL MEMORY CELL STRING WITH A WEIGHTING ELECTRODE TO INCREASE MEMORY CAPACITY, A MEMORY ARRAY USING THE SAME, AND A MANUFACTURING METHOD THEREOF

机译:带有加权电极的3D垂直存储单元字符串,用于增加存储容量,使用相同存储空间的存储阵列及其制造方法

摘要

PURPOSE: A 3D vertical memory cell string with a weighting electrode, a memory array including the same, and a manufacturing method thereof are provided to remove interference between bodies by including a weighting control electrode, a tunneling insulation layer, and the weighting electrode between adjacent cell stacks sharing the body.;CONSTITUTION: Two or more electrode stacks(40) are formed on a semiconductor substrate(1). A semiconductor body(5) is formed on a gate insulation layer stack. A first separation insulation layer(6) is formed between a weighting electrode(27) and the semiconductor body. A second separation insulation layer(28) electrically separates each weighting electrode in each trench direction. A tunneling insulation layer(29) is formed on each weighting electrode.;COPYRIGHT KIPO 2013
机译:目的:提供一种具有配重电极的3D垂直存储单元串,包括该3D垂直存储单元串的存储阵列及其制造方法,以通过在相邻之间包括配重控制电极,隧穿绝缘层和配重电极来消除物体之间的干扰。组成:构成:在半导体衬底(1)上形成两个或多个电极堆栈(40)。在栅极绝缘层堆叠上形成半导体本体(5)。在权重电极(27)和半导体本体之间形成第一隔离绝缘层(6)。第二分离绝缘层(28)在每个沟槽方向上电分离每个加权电极。在每个称重电极上形成一个隧道绝缘层(29)。; COPYRIGHT KIPO 2013

著录项

  • 公开/公告号KR20130014990A

    专利类型

  • 公开/公告日2013-02-12

    原文格式PDF

  • 申请/专利权人 SNU R&DB FOUNDATION;

    申请/专利号KR20110076775

  • 发明设计人 LEE JONG HO;

    申请日2011-08-01

  • 分类号H01L27/115;H01L21/8247;

  • 国家 KR

  • 入库时间 2022-08-21 16:27:45

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