FAILURE DETECTION METHOD FOR LOGIC CIRCUIT, TEST CIRCUIT INSERTION METHOD, TEST CIRCUIT INSERTION DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To detect a delay failure of a signal path including one input of a logic gate and a delay failure of a signal path including the other input of the logic gate by a single control point.;SOLUTION: A logic circuit includes first and second user logics, a first logic gate having a first input connected to the output of the first user logic, a third user logic connected to the output of the first logic gate, and a control point inserted between the second user logic and first logic gate. The control point has a second scan flip-flop in which one data output of a first scan flip-flop of the first or third user logic is connected to a data input, and a second logic gate having a pair of inputs connected to a data output of the second scan flip-flop and an output of the second user logic respectively and also having an output connected to a second input of the first logic gate.;COPYRIGHT: (C)2013,JPO&INPIT