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Testability analysis and insertion for RTL circuits based on pseudorandom BIST

机译:基于伪随机BIST的RTL电路的可测试性分析和插入

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摘要

A testability analysis technique for built-in self-test (BIST) at the system level is presented. While based on previous approaches, the model has several significant new features, including an iterative technique for modeling indirect feedback and an extension to the circular BIST methodology. Additionally, a new preprocessing transformation enables the correct modeling of word-level correlation. Examples validate the model, and demonstrate its applicability to test point insertion.
机译:提出了一种用于系统级内置自测(BIST)的可测试性分析技术。尽管基于以前的方法,该模型具有几个重要的新功能,包括用于对间接反馈进行建模的迭代技术以及对循环BIST方法的扩展。此外,新的预处理转换可对词级相关性进行正确的建模。实例验证了该模型,并演示了其在测试点插入中的适用性。

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