Testability Analysis and Insertion for RTL Circuits Based on Pseudorandom BIST

摘要

A testability analysis technique for Built-in Self-Test (BIST) at the system level is presented. While based on previous approaches, the model has several significant new features, including an iterative technique for modeling indirect feedback and an extension to the circular BIST methodology. Additionally, a new preprocessing transformation enables the correct modeling of word-level correlation. Examples validate the model, and demonstrate its applicability to test point insertion.