ALARM-BASED POWER SAVING MODE FOR AN ELECTRONIC DEVICE

摘要

This disclosure relates to an alarm-based power saving mode and associated system implemented on a device for a microprocessor or a telematics circuitry, and more particularly, to an alarm and powered-up microprocessor-driven power latch for disabling a power source to a microprocessor or telematics circuitry at a power switch. A microprocessor and/or telematics circuitry are powered down by an instruction step from the microprocessor or the telematics circuitry by using a power switch to cut off power. The switch is controlled by a power latch, which is regulated by a wake-up value given to an alarm to enable the power latch and exercise power switch control, as well as by a value given directly by the microprocessor to enter the powered down mode.