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STRUCTURE AND METHOD FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
STRUCTURE AND METHOD FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
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机译:焊点集成电路层间介电层中应力诱发故障的监测结构和方法
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摘要
A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.
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