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Changing abstraction level of portion of circuit design during verification
Changing abstraction level of portion of circuit design during verification
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机译:验证期间更改电路设计部分的抽象级别
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摘要
A design verification method is disclosed. A computer searches for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks. Then, the computer changes an abstraction level of an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist.
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