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Non-Volatile Latch Circuit And Logic Circuit, And Semiconductor Device Using The Same

机译:非易失性锁存电路和逻辑电路,以及使用其的半导体器件

摘要

A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.
机译:提供了新颖的非易失性锁存电路和使用该非易失性锁存电路的半导体器件。锁存电路具有环路结构,其中第一元件的输出电连接到第二元件的输入,并且第二元件的输出通过第二晶体管电连接到第一元件的输入。使用氧化物半导体作为沟道形成区域的半导体材料的晶体管用作开关元件,并且提供电容器以电连接到晶体管的源电极或漏电极,由此锁存电路的数据可以保留,从而可以形成非易失性锁存电路。

著录项

  • 公开/公告号US2013057315A1

    专利类型

  • 公开/公告日2013-03-07

    原文格式PDF

  • 申请/专利权人 SEMICONDUCTOR ENERGY LABORATORY CO. LTD.;

    申请/专利号US201213667292

  • 发明设计人 KIYOSHI KATO;JUN KOYAMA;

    申请日2012-11-02

  • 分类号H03K19/173;

  • 国家 US

  • 入库时间 2022-08-21 16:46:54

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