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Cache controller, method for controlling the cache controller, and computing system comprising the same
Cache controller, method for controlling the cache controller, and computing system comprising the same
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机译:高速缓存控制器,用于控制高速缓存控制器的方法以及包括该高速缓存控制器的计算系统
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摘要
A cache controller, a method for controlling the cache controller, and a computing system comprising the same are provided. The computer system comprises a processor and a cache controller. The cache controller is electrically connected to the processor and comprises a first port, a second port, and at least one cache. The first port is configured to receive an address of a content, wherein a type of the content is one of instruction and data. The second port is configured to receive an information bit corresponding to the content, wherein the information bit indicates the type of the content. The at least one cache comprises at least one cache lines. Each of the cache lines comprises a content field and corresponding to an information field. The content and the information bit is stored in the content field of one of the cache lines and the corresponding information field respectively according to the information bit and the address. Thereby, instruction and data are separated in a unified cache.
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