Design of Cache Controller for Multi-core Systems using Multilevel Scheduling Method

摘要

Now a days, Multicore processor are utilized as a major development platform for real time system to achieve better processing performance. Multicore processor, which having multiple processing unite on a single chip, attracting the researcher to work for improvement of time performance and power consumption of the system. Many algorithms are proposed by researcher for improvement in time and power consumption, still there is a wide scope to propose and implement in the area. Cache handling is such issue to be sited less but having more impact on the performance of Multi-core systems. Once of the prominent issue in the multicore processor system is cache coherence. Hence there is a need to be implementing a suitable and efficient method or design to handle. Here Author is proposing a new concept of cache controlling by multilevel scheduling method, which utilized the concept of priority scheduling followed by round robin scheduling. The proposed system is modeled using hardware descriptive language and simulation results are presented.