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Statistical iterative timing analysis of circuits having latches and/or feedback loops
Statistical iterative timing analysis of circuits having latches and/or feedback loops
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机译:具有锁存器和/或反馈回路的电路的统计迭代时序分析
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摘要
Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.
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