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Flexible CMOS library architecture for leakage power and variability reduction
Flexible CMOS library architecture for leakage power and variability reduction
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机译:灵活的CMOS库架构,可降低泄漏功率并降低可变性
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摘要
The present invention relates to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.
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