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Integrated circuit chip with a stress buffering layer, semiconductor device, method for protecting a chip and single chip device

机译:具有应力缓冲层的集成电路芯片,半导体器件,保护芯片的方法和单芯片器件

摘要

An integrated circuit chip configured to be mounted on a carrier, the integrated circuit chip comprising: a first surface configured to be mounted on the carrier; an active area of the integrated circuit chip spaced from the first surface; a bondpad disposed over the active area and in electrical communication therewith; and a ceramic inorganic stress buffering layer disposed between the active region and the bonding pad, wherein the stress buffering layer comprises nitrides of one of Group 4-6 of the Periodic Table of Elements, borides of one of Groups 4-6 or carbides of one of the groups 4-6 covers.
机译:一种集成电路芯片,被配置为安装在载体上,该集成电路芯片包括:第一表面,其被配置为安装在载体上;集成电路芯片的有源区域与第一表面间隔开;接合垫,其布置在有源区域上方并与其电连通;设置在有源区和键合焊盘之间的陶瓷无机应力缓冲层,其中该应力缓冲层包含元素周期表4-6族之一的氮化物,4-6族之一的硼化物或一种碳化物4-6组中的一组。

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