首页> 外国专利> Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module

Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module

机译:通过从具有电路互连的连续堆积层制造封装模块并在封装模块的顶面上形成空腔来封装集成电路

摘要

An integrated circuit (IC) is packaged by fabricating a package module from successive build-up layers having circuit interconnections; forming a cavity on a top-side of package module; attaching a metallized back-side of a chip having front-side with a forward contact onto a metallic layer; disposing the chip in cavity such that forward contact is connected to the circuit interconnections of package module; and coupling the metallic layer that is attached to the chip onto the top-side of the package module. An independent claim is included for an IC package.
机译:通过从具有电路互连的连续堆积层制造封装模块来封装集成电路(IC)。在封装模块的顶侧上形成空腔;将芯片的金属化的背面(具有正面且具有向前的接触)附着到金属层上;将芯片布置在空腔中,使得正向触点连接到封装模块的电路互连;将附着在芯片上的金属层耦合到封装模块的顶侧。 IC封装中包含独立索赔。

著录项

  • 公开/公告号DE102012112328A1

    专利类型

  • 公开/公告日2013-06-20

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE201210112328

  • 发明设计人 DAECHE FRANK;MEYER-BERG GEORG;

    申请日2012-12-14

  • 分类号H01L23/492;H01L23/498;H01L23/538;H01L21/58;

  • 国家 DE

  • 入库时间 2022-08-21 16:21:50

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