A memory cell has a first word - line in a first connecting layer, a first vss - line, a first bit line, a power source line, a second bit line, a second vss - line, which in a second connecting layer is formed, and a second word - line in a third connection layer. The memory cell has, furthermore, a word - line strip structure on which, between the power source line and the second bit line is provided, wherein the word - line strip structure, the first word - line with the second word - line connects.
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