A method of manufacturing a low leakage DRAM memory cell with a vertical alignment nanorods

摘要

Method and structure in order to decrease leak electric current in the semiconductor memory storage cell are stated. The vertical orientation nano- rod (403) can be used, the access transistor (400) in the channel territory. As for diameter of the nano- rod, it is possible to make sufficiently small in order to cause the increase of electronic band gap energy inside the channel territory of the access transistor this can do in order to restrict the channel leak electric current in off state, function. With various execution forms, the both sides capacitor (425) it can connect the access transistor electrically. Also the system which includes the memory device, and that kind of device which you follow the execution form of this invention is disclosed and.