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Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process
Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process
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机译:使用替代栅极工艺制造的纳米线FET中的压缩(PFET)和拉伸(NFET)沟道应变
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摘要
A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
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