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METHOD FOR MANUFACTURING DUMMY GATE IN GATE LAST PROCESS AND DUMMY GATE IN GATE LAST PROCESS

机译:门最后过程中的虚拟门和门最后过程中的虚拟门的制造方法

摘要

Provided are a method for manufacturing a dummy gate in a gate last process and a dummy gate in a gate last process. The method comprises: providing a semiconductor substrate (20); growing a gate oxide layer (22) on the semiconductor substrate (20); depositing a bottom-layer amorphous silicon (24) on the gate oxide layer (22); depositing an oxide film/nitride film/oxide film (ONO) structure hard mask (26) on the bottom-layer amorphous silicon (24); depositing a top-layer amorphous silicon (28) on the ONO structure hard mask (26); depositing a hard mask layer (30) on the top-layer amorphous silicon (28); forming a photoresist line (32) on the hard mask layer (30), and miniaturizing the formed photoresist line (32), so that the width of the miniaturized photoresist line is smaller than and equal to 22 nm; and etching the hard mask layer (30), the top-layer amorphous silicon (28), the ONO structure hard mask (26) and the bottom-layer amorphous silicon (24) by using the photoresist line (32) as a standard, and removing the photoresist line (32), the hard mask layer (30) and the top-layer amorphous silicon (28). Therefore, the critical size and sectional profile of the gate can be precisely controlled, the roughness of the gate line can be effectively improved, and the performance and stability of the device can be ensured.
机译:提供了一种在后栅极工艺中制造伪栅极和在后栅极工艺中制造伪栅极的方法。该方法包括:提供半导体衬底(20);在半导体衬底(20)上生长栅氧化层(22);在栅极氧化物层(22)上沉积底层非晶硅(24);在底层非晶硅(24)上沉积氧化物膜/氮化物膜/氧化物膜(ONO)结构的硬掩模(26);在ONO结构硬掩模(26)上沉积顶层非晶硅(28);在顶层非晶硅(28)上沉积硬掩模层(30);在硬掩模层(30)上形成光致抗蚀剂线(32),并使形成的光致抗蚀剂线(32)小型化,以使小型化的光致抗蚀剂线的宽度小于等于22nm。然后,以光致抗蚀剂线(32)为基准,对硬掩模层(30),顶层非晶硅(28),ONO结构硬掩模(26)以及底层非晶硅(24)进行蚀刻,去除光刻胶线(32),硬掩模层(30)和顶层非晶硅(28)。因此,可以精确地控制栅极的临界尺寸和截面轮廓,可以有效地改善栅极线的粗糙度,并且可以确保器件的性能和稳定性。

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