GaN high voltage HFET with passivation plus gate dielectric multilayer structure

摘要

A method of fabricating a multi-layer structure for a power transistor device includes exposing, within a reaction chamber, a top surface of a nitride-based active semiconductor layer to a first source, and performing, within the reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer (142) directly on the nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer (145) directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.