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METHOD FOR FORMING A multilevel copper interconnect of integrated circuit with a tungsten hard mask

机译:形成具有钨硬掩模的集成电路的多层铜互连的方法

摘要

1. A method for forming multilevel interconnections of copper on VLSI process double Damascena through rigid bilayer mask comprising applying an insulating dielectric layer on a plate, in the body which will form the conductors of the integrated circuit, application of the insulating dielectric over the lower two-layer hard mask layer of silicon dioxide and a top layer two-layer rigid mask on the top layer forming the hard mask bilayer topological mask of resist, etching the upper layer of the two-layer rigid wt ki and the lower layer two-layer hard mask silicon dioxide through the resist layer, removing the residual resist from the surface of the formed two-layer hard mask, etching grooves and transition of the contact holes in a layer of insulating dielectric, filling the formed grooves and transition contact windows layer of metallization and removing excess volume of the supported metal with surface plates, characterized in that as a material of the upper layer using the hard mask layer volframa.2. The method of claim. 1, characterized in that the thickness of the upper layer tungsten hard mask bilayer is from 25 nm to 100 nm.
机译:1.一种通过刚性双层掩模在VLSI工艺双大马士革上形成铜的多层互连的方法,包括在板上形成绝缘电介质层,该绝缘电介质层将形成集成电路的导体,并在下部形成绝缘电介质。二氧化硅的两层硬掩模层和在顶层上的顶层两层刚性掩模,形成抗蚀剂的硬掩模双层拓扑掩模,刻蚀两层刚性wt ki的上层和下层两层通过抗蚀剂层形成一层硬掩模二氧化硅,从形成的两层硬掩模的表面上去除残留的抗蚀剂,在绝缘电介质层中刻蚀沟槽和接触孔的过渡部分,填充形成的沟槽和过渡接触窗口层金属化和用面板去除多余的支撑金属,其特征在于,使用硬掩模作为上层材料层体积2。权利要求的方法。如图1所示,其特征在于,上层钨硬掩模双层的厚度为25nm至100nm。

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