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INTEGRATED COMPARATOR HYSTERESIS, ESPECIALLY IN FD SOI TECHNOLOGY
INTEGRATED COMPARATOR HYSTERESIS, ESPECIALLY IN FD SOI TECHNOLOGY
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机译:集成比较器迟滞,特别是在FD SOI技术中
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摘要
The hysteresis is obtained by the threshold voltage difference between MOS transistors (T5, T6) having their boxes (CS5, CS6) directly biased by the signal outputs (NOUT, OUT) of the output stage.
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