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ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING
ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING
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机译:使用片上时钟进行ATPG设计失败的实时测试和调试逻辑
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摘要
A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.
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机译:半导体芯片包括OCC,该OCC接收ATPG测试图案并作为响应产生时钟脉冲。 OCC测试电路检测OCC电路的时钟脉冲,并提供调试数据以测试输出可配置逻辑,该逻辑也接收来自测试不同DUT触发器的其他电路的结果。削波测试电路通过向DUT I / O提供对脉冲宽度敏感的触发器输出,来检测由于来自OCC的削波时钟脉冲而导致的ATPG故障。 IR跌落测试电路检测ATPG故障是否是由于某些触发器中的IR跌落问题引起的。脉冲位操作电路改变提供给OCC和OCC生成的时钟脉冲的测试模式。连接到测试输出可配置逻辑的调试控制器在不同测试的结果之间进行选择,以提供作为输出测试信号,以便与ATE上的预期模式数据进行即时比较,并用于隔离芯片上的错误。
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