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On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
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机译:使用片上时钟对设计的ATPG故障进行实时测试和调试逻辑
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摘要
A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.
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