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METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING TOPOGRAPHICAL FEATURES FOR DIRECTED SELF-ASSEMBLY

机译:一种直接自组装的包括拓扑特征的集成电路的制造方法

摘要

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.
机译:提供了制造集成电路的方法。在一个示例中,一种用于制造集成电路的方法包括形成覆盖半导体衬底的抗蚀刻填充控制形貌特征。耐腐蚀填充控制的形貌特征限定了耐腐蚀填充控制的限制井。将嵌段共聚物沉积到抗蚀刻填充控制限制孔中。将该嵌段共聚物相分离成可蚀刻相和耐蚀刻相。耐蚀刻填充控制的形貌特征指导耐蚀刻相在耐蚀刻填充控制限制井中形成耐蚀刻塞。

著录项

  • 公开/公告号US2015126034A1

    专利类型

  • 公开/公告日2015-05-07

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201314072149

  • 发明设计人 EDWARD TEOH KAH CHING;HE YI;AZAT LATYPOV;

    申请日2013-11-05

  • 分类号H01L21/02;H01L21/306;

  • 国家 US

  • 入库时间 2022-08-21 15:21:27

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