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Method of forming group III-V material layer, semiconductor device including the group III-V material layer, and method of manufacturing the semiconductor layer

机译:形成III-V族材料层的方法,包括III-V族材料层的半导体器件以及制造该半导体层的方法

摘要

A method of forming a group III-V material layer, a semiconductor device including the group III-V material layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate; a group III-V channel layer formed on the substrate; a gate insulating layer formed on the group III-V channel layer; and a gate electrode and source and drain electrodes formed on the gate insulating layer, the source and drain electrodes having intervals from the gate electrode, wherein voids exist between a lower portion of the group III-V channel layer and an insulating layer. The group III-V channel layer may include a binary, ternary, or quaternary material.
机译:形成III-V族材料层的方法,包括III-V族材料层的半导体器件以及制造该半导体器件的方法。该半导体器件包括衬底;和衬底。在衬底上形成的III-V族沟道层;在III-V族沟道层上形成的栅极绝缘层;在栅极绝缘层上形成有栅电极以及源电极和漏电极,该源电极和漏电极与栅电极具有间隔,其中在III-V族沟道层的下部与绝缘层之间存在空隙。 III-V族沟道层可以包括二元,三元或四元材料。

著录项

  • 公开/公告号US8956936B2

    专利类型

  • 公开/公告日2015-02-17

    原文格式PDF

  • 申请/专利权人 SANG-MOON LEE;YOUNG-JIN CHO;

    申请/专利号US201213568555

  • 发明设计人 SANG-MOON LEE;YOUNG-JIN CHO;

    申请日2012-08-07

  • 分类号H01L29/78;H01L29/10;H01L29/423;H01L29/778;

  • 国家 US

  • 入库时间 2022-08-21 15:20:06

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