Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

摘要

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.