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USE OF CONFORMAL COATING ELASTIC CUSHION TO REDUCE THROUGH SILICON VIAS (TSV) STRESS IN 3-DIMENSIONAL INTEGRATION
USE OF CONFORMAL COATING ELASTIC CUSHION TO REDUCE THROUGH SILICON VIAS (TSV) STRESS IN 3-DIMENSIONAL INTEGRATION
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机译:在3维集成中使用保形涂层弹性垫减少硅通孔(TSV)应力
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摘要
Integrated circuit assemblies, as well as methods for creating the same, are provided. The integrated circuit assembly includes a first chip and a second chip, including respective face surfaces, wherein the first chip and the second chip are bonded in a face-against-face contact configuration. The integrated circuit assembly includes a via disposed to pass through the first chip and the second chip. The via is surrounded by at least one material of the respective first chip and the second chip. A cushion layer encapsulating at least a portion of the via is formed between the via and the at least one material surrounding the via.
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