Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories

摘要

A memory error detection circuit is provided. The circuit arrangement comprises a memory (11) and an error detection circuit (12). The circuit arrangement is designed to store a code word of an error-detecting code (C) or a code word inverted in a subset (M) of bits in the memory (11) at a memory location and to read a data word from the memory (11) from the memory location , The error detection circuit (12) is adapted to indicate a memory error in the event that an applied control signal assumes a first value, if the data word is not a code word of the error-detecting code (C). Further, the error detection circuit (12) is adapted, in the case where the applied control signal assumes a second value other than the first value, and to the memory location the codeword inverted in the subset (M) of bits has been written the data word read from the memory (11) to determine whether there is a memory error when the codeword inverted in the subset (M) of bits is not a codeword of the error-detecting code (C).