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Method and apparatus for congestion aware buffering using power supply isolation pathway for integrated circuit design with multiple power domains
Method and apparatus for congestion aware buffering using power supply isolation pathway for integrated circuit design with multiple power domains
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机译:使用电源隔离路径进行拥塞感知缓冲的方法和装置,用于具有多个电源域的集成电路设计
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摘要
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
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