METHODS AND APPARATUS FOR CONGESTION AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI POWER DOMAINS

摘要

A semiconductor apparatus is provided herein for buffering of nets (412) routed through one or more areas associated with a first power domain (452) that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the b uffered nets to be determined not only based on the shortest distance to travel from Point A to Point B but also takes into account routing congestion on the semiconductor apparatus. Consequently if an area on the semiconductor apparatus is congested the buffered nets may be routed around the congestion. As such although a path taken by a particular signal through the integrated circuit is not a direct route it may still be of a distance to support a speed at which the particular signal needs to be transferred.