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REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS
REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS
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机译:减少具有低有效质量通道的场效应晶体管中的直接源漏隧道
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摘要
An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
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