首页> 外国专利> Semiconductor Device and Method of Forming Conductive Vias by Backside Via Reveal with CMP

Semiconductor Device and Method of Forming Conductive Vias by Backside Via Reveal with CMP

机译:半导体装置和利用CMP露出背面通孔形成导电通孔的方法

摘要

A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.
机译:半导体器件具有半导体晶片和穿过半导体晶片形成的导电通孔。去除半导体晶片的一部分,使得导电通孔的一部分在半导体晶片上方延伸。在导电通孔和半导体晶片上方形成第一绝缘层。在第一绝缘层上方形成第二绝缘层。第一绝缘层包括无机材料,第二绝缘层包括有机材料。通过化学机械抛光(CMP)同时从导电通孔上方去除第一绝缘层和第二绝缘层的一部分。可替代地,在导电通孔和半导体晶片上方形成包括有机材料的第一绝缘层。通过CMP去除第一绝缘层的一部分。在导电通孔和第一绝缘层上方形成导电层。导电层基本上是平面的。

著录项

  • 公开/公告号US2015380339A1

    专利类型

  • 公开/公告日2015-12-31

    原文格式PDF

  • 申请/专利权人 STATS CHIPPAC LTD.;

    申请/专利号US201414316561

  • 申请日2014-06-26

  • 分类号H01L23/48;H01L21/306;H01L25/065;H01L21/78;H01L25;H01L21/768;H01L21/3105;

  • 国家 US

  • 入库时间 2022-08-21 14:32:52

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