首页> 外国专利> Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region

机译:在半导体衬底中形成高纵横比的沟槽和具有高纵横比的沟槽隔离区的双极半导体器件

摘要

Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.
机译:公开了一种沟槽形成技术,其中第一蚀刻工艺形成穿过半导体层进入半导体衬底的开口,然后第二蚀刻工艺扩展衬底内的开口的一部分以形成沟槽。然而,在第二蚀刻之前,在开口的底表面处的衬底中形成掺杂区。然后,执行第二蚀刻,使得以比掺杂区域更快的蚀刻速率蚀刻在开口的侧壁处的基板的未掺杂区域,从而确保沟槽具有相对高的纵横比。还公开了双极半导体器件的形成方法。该方法结合了沟槽形成技术,使得围绕集电极基座形成的沟槽隔离区域具有高的纵横比,从而集电极-基极电容C cb 和集电极电阻R c 均已最小化。

著录项

  • 公开/公告号US9224843B2

    专利类型

  • 公开/公告日2015-12-29

    原文格式PDF

  • 申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;

    申请/专利号US201514673958

  • 发明设计人 JOHN J. BENOIT;QIZHI LIU;JAMES R. ELLIOTT;

    申请日2015-03-31

  • 分类号H01L29/73;H01L29/737;H01L29/66;H01L29/06;H01L21/265;H01L21/306;H01L21/465;H01L21/762;H01L29/165;H01L29/732;

  • 国家 US

  • 入库时间 2022-08-21 14:28:26

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