SUBSTRATE LESS INTERPROSER TECHNOLOGY FOR A STACKED SILICON INTERCONNECT TECHNOLOGY

摘要

A substrate less interposer (201) for a stacked silicon interconnect technology (SSIT) product (200) includes: a plurality of metallization layers (109) at least a bottom most layer of the metallization layers comprising a plurality of metal segments (111) wherein each of the plurality of metal segments (111) is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers (109) and the metal segments (111) are separated by dielectric material (113) in the bottom most layer; and a dielectric layer (203) formed on the bottom surface of the bottom most layer wherein the dielectric layer (203) includes one or more openings for providing contact to at least some of the plurality of metal segments (111) in the bottom most layer.