MONOLITHIC THREE DIMENSIONAL (3D) FLIP FLOPS WITH MINIMAL CLOCK SKEW AND RELATED SYSTEMS AND METHODS

摘要

Monolithic three dimensional (3D) flip flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier thus potentially giving better setup hold and clock to q margin. In particular a first tier of the 3DIC has the master latch slave latch and clock circuit. A second tier has the input circuit and the output circuit.