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Non-planar semiconductor device with self-aligned ridge with upper barrier layer

机译:具有自对准脊和上阻挡层的非平面半导体器件

摘要

Non-planar semiconductor devices with self-aligned lands with top barrier layers and methods for fabricating non-planar semiconductor devices with self-aligned lands with top barrier layers are described. For example, a semiconductor structure includes a semiconductor fin having a top surface disposed above a semiconductor substrate. On both sides of the semiconductor fin, an insulating layer is disposed and recessed under the upper surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the upper surface. A gate barrier layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer merges into the second portion of the gate barrier layer but is thicker than the second portion. A gate stack is disposed on the first and second portions of the gate blocking layer.
机译:描述了具有具有顶部阻挡层的自对准焊盘的非平面半导体器件以及用于制造具有具有顶部阻挡层的自对准焊盘的非平面半导体器件的方法。例如,半导体结构包括半导体鳍,该半导体鳍具有布置在半导体衬底上方的顶表面。在半导体鳍的两侧上,布置绝缘层并使其凹陷在半导体鳍的上表面下方,以提供半导体鳍的突出部分。突出部分具有侧壁和上表面。栅阻挡层具有布置在半导体鳍的顶表面的至少一部分上的第一部分和具有布置在半导体鳍的侧壁的至少一部分上的第二部分。栅极阻挡层的第一部分合并到栅极势垒层的第二部分中,但是比第二部分厚。栅极堆叠设置在栅极阻挡层的第一和第二部分上。

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