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Integrated circuits with the vertical connection between nfets and pfets and method for producing the same

机译:nfet和pfets之间具有垂直连接的集成电路及其制造方法

摘要

There are integrated circuits and methods for making available the same. A method for fabricating an integrated circuit comprises a form of an implantation mask, which a dummy - gate is superimposed, in the implantation mask a masked dummy - gate and a free-floating dummy - gate forms. In the exposed dummy - gate ions are implanted and the implantation mask is removed. The masked dummy - gate g is etched with an etchant which, with respect to the masked dummy - gate via the exposed dummy - gate is selective, in order to form a trench, and the trench is filled with a conductive material.
机译:有集成电路和使其可用的方法。一种用于制造集成电路的方法,其包括注入掩模的形式,在该掩模上叠置了伪栅极,在该注入掩模中,形成了掩蔽的伪栅极和自由浮动的伪栅极形式。在暴露的伪器件中,注入栅离子,并去除注入掩模。用蚀刻剂蚀刻掩模的伪栅极g,该蚀刻剂相对于掩模的伪栅极经由暴露的伪栅极是选择性的,以形成沟槽,并且沟槽填充有导电材料。

著录项

  • 公开/公告号DE102015200593A1

    专利类型

  • 公开/公告日2015-12-17

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号DE201510200593

  • 发明设计人 PETER BAARS;HANS-PETER MOLL;

    申请日2015-01-16

  • 分类号H01L21/8238;H01L21/265;H01L27/092;

  • 国家 DE

  • 入库时间 2022-08-21 14:09:24

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