Method of tunnel oxide layer formation and related devices in a three-dimensional NAND memory structure

摘要

A three-dimensional NAND memory structure and associated method are provided. In some embodiments, the plurality of structures includes a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, and an interpoly dielectric (IPD). An IPD layer disposed between the floating gate material and the control gate material and deposited on the floating gate material opposite the control gate material so that the layer electrically isolates the control gate material from the floating gate material. Tunnel dielectric material.