Scan Logic For Circuit Designs With Latches And Flip-Flops

摘要

A system for scanning a circuit includes flip-flops and latches includes a multiplexer to couple an output of a flip-flop with an input of a latch. The multiplexer has an input receiving an input signal for the latch and another input coupled with output of the flip-flop. The system further another multiplexer to couple output of the first multiplexer with an input of another flip-flop. The system also includes scan logic for controlling multiplexers to load test data into the flip-flop and into the latch from the flip-flop. The system also includes scan logic for passing output of the flip-flop and the latch into portions of the circuit to be tested.